EE 2. 01. A/EE2. 01. BModeling and Optimization for VLSI Layout. Spring. DEPARTMENT OF ELECTRICAL ENGINEERINGTime: 1. TR Place: 5. 43. 6 Boulter Instructor. Lei He. Department of Electrical Engineering. Office: 6. 20. 37 Engineering IVPhone: 2. E- Mail: lhe@ee. ucla. Partitioning and clustering ppt Reading. Shekhar, 'Multilevel Hypergraph Partitioning: Application in VLSI Domain', Proceedings of the Design Automation. ACM/IEEE Design Automation Conference. Course Outline and Schedule. Front- end physical design (4. Paritioning, floorplanning and placement. Power and thermal modeling. Algorithms: divided and conquer, simulated annealing, genetic algorithm. Back- end physical design (4. Interconnect extraction and modeling. Interconnect synthesis. Noise modeling and avoidance. Clock and power supply design. Algorithms: dynamic programming, linear programming. Project report due the last day of the quarter. Grading Policy: 1. Student Presentation: 2~3 student a team. Survey an area (topics and resources specified by me on a continual basis). Prepare slides and do a 3. I will select the speaker randomly at the presentation time. Prepare a web site that should contain a report based on your survey, a bibliography, and links to resources and of course your slides. Topics and Schedule. Course Project: Programming Homework: 3. D packing. Lecture Notes. Chapter 1: Introduction ppt. Chapter 2: Partitioning and clustering ppt.
Was this review helpful to you? Yes No Sending feedback. Introduction to VLSI Design methodologies, Review of Data structures and algorithms, Review of VLSI Design automation tools. PPT 3 Review of VLSI Design Automation Tools 1-Ch-2; pg (11-19) PPT 4 Design Style 2-Ch-1; pg (15-25). Reading. B. Proceedings of the Design Automation Conference, pp 1. IEEE Transactions on Computer- Aided Design, Vol. Design Automation Conference, pp 1. DAC, pp 4. 27- 4. Stan. Karthik Sankaranarayanan. Shougata Ghosh. Sivakumar Velusamy. Nakagawa. . IEEE International Conference on Computer Aided Design, San Jose, California, pp. November 2. 00. 1. J. Asia South Pacific Design Automation Conference (ASPDAC), Jan. Pacifico Yokohama, Japan. Chapter 1. 2: Review and take home exam. 2013 204424 Digital Design Automation 58 Review - VLSI Levels of Abstraction. Design automation engineer PDF. This preview shows document pages 1.
0 Comments
Leave a Reply. |
Details
AuthorWrite something about yourself. No need to be fancy, just an overview. Archives
November 2016
Categories |